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IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW PLL CLOCK DRIVER TURBOCLOCKTM JR.
FEATURES:
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IDT59920A
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Eight zero delay outputs Selectable positive or negative edge synchronization Synchronous output enable Output frequency: 15MHz to 100MHz CMOS outputs 3 skew grades: IDT59920A-2: tSKEW0<250ps IDT59920A-5: tSKEW0<500ps IDT59920A-7: tSKEW0<750ps 3-level inputs for PLL range control PLL bypass for DC testing External feedback, internal loop filter 46mA IOL high drive outputs Low Jitter: <200ps peak-to-peak Outputs drive 50 terminated lines Pin-compatible with Cypress CY7B9920 Available in SOIC package
The IDT59920A is a high fanout phase lock loop clock driver intended for high performance computing and data-communications applications. The IDT59920A has CMOS outputs. The IDT59920A maintains Cypress CY7B9920 compatibility while providing two additional features: Synchronous Output Enable (GND/ sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/sOE pin is held low, all outputs are synchronously enabled (CY7B9920 compatibility). However, if GND/sOE is held high, all outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VDDQ/PE is held high, all outputs are synchronized with the positive edge of the REF clock input (CY7B9920 compatibility). When VDDQ/PE is held low, all outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
VDDQ/PE G ND/sOE Q0 Q1
Q2 Q3 PLL REF Q4 Q5 FS Q6 Q7
FB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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c 2001 Integrated Device Technology, Inc.
SEPTEMBER 2001
DSC 5846/2
IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VI TSTG Description Supply Voltage to Ground DC Input Voltage Maximum Power Dissipation (TA = 85C) Storage Temperature Max -0.5 to +7 -0.5 to +7 530 -65 to +150 Unit V V mW C
REF VDDQ FS NC VDDQ/PE VDDN Q0 Q1 GND Q2 Q3 VDDN
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
GND TEST NC GND/sOE VDDN Q7 Q6 GND Q5 Q4 VDDN FB
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance Typ. 5 Max. 7 Unit pF
SOIC TOP VIEW
NOTE: 1. Capacitance applies to all inputs except TEST and FS. It is characterized but not production tested.
PIN DESCRIPTION
Pin Name REF FB TEST (1) GND/ sOE(1) VDDQ/PE FS(2) Type IN IN IN IN IN IN Description Reference Clock Input Feedback Input When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Frequency range select. 3 level input. FS = GND: 15 to 35MHz FS = MID (or open): 25 to 60MHz FS = VDD: 40 to 100MHz Q0 - Q7 VDDN VDDQ GND OUT PWR PWR PWR Eight clock output Power supply for output buffers Power supply for phase locked loop and other internal circuitry Ground
NOTES: 1. When TEST = MID and GND/sOE = HIGH, PLL remains active. 2. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved.
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IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
IDT59920A-5, -7 (Industrial) Symbol VDD TA Description Power Supply Voltage Ambient Operating Temperature Min. 4.5 -40 Max. 5.5 +85 IDT59920A-2 (Commercial) Min. 4.75 0 Max. 5.25 +70 Unit V C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIH VIL VIHH VIMM VILL IIN Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Voltage(1) Input MID Voltage
(1)
Conditions Guaranteed Logic HIGH (REF, FB Inputs Only) Guaranteed Logic LOW (REF, FB Inputs Only) 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD or GND VDD = Max. VIN = VDD HIGH Level MID Level LOW Level
Min. VDD-1.35 -- VDD-1 VDD/2-0.5 -- -- -- -- -- -- -- -- VDD-0.75 -- --
Max. -- 1.35 -- VDD/2+0.5 1 5 200 50 200 100 100 -- -- 0.45 N/A
Unit V V V V V A
Input LOW Voltage(1) Input Leakage Current (REF, FB Inputs Only)
I3 IPU IPD VOH VOL IOS
3-Level Input DC Current (TEST, FS) Input Pull-Up Current (VDDQ/PE) Input Pull-Down Current (GND/sOE) Output HIGH Voltage Output LOW Voltage Output Short Circuit Current
(2)
VIN = VDD/2 VIN = GND VDD = Max., VIN = GND VDD = Max., VIN = VDD VDD = Min., IOH = -16mA VDD = Min., IOH = -40mA VDD = Max., VO = GND VDD = Min., IOL = 46mA
A A A V V mA
NOTES: 1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. Outputs are not to be shorted.
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDD IDDD ITOT Parameter Quiescent Power Supply Current Power Supply Current per Input HIGH Dynamic Power Supply Current per Output Total Power Supply Current Test Conditions(1) VDD = Max., TEST = MID, REF = LOW, GND/sOE = LOW, All outputs unloaded VDD = Max., VIN = 3.4V VDD = Max., CL = 0pF VDD = 5V, FREF = 25MHz, CL = 240pF(1) VDD = 5V, FREF = 33MHz, CL = 240pF(1) VDD = 5V, FREF = 66MHz, CL =
NOTE: 1. For eight outputs, each loaded with 30pF.
Typ. 10 0.4 100 53 63 117
Max. 40 1.5 160 -- -- --
Unit mA mA A/MHz mA
240pF(1)
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IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol tR, tF tPWC DH REF Description (1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference Clock Input Min. -- 3 10 15 Max. 10 -- 90 100 Unit ns/V ns % MHz
NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT59920A-2 Symbol Parameter FS = LOW FREF tRPWH tRPWL tSKEW0 tDEV tPD tODCV tORISE tOFALL tLOCK tJR REF Frequency Range REF Pulse Width HIGH
(1,8)
IDT59920A-5 Max. 35 60 100 -- -- 0.25 0.75 0.25 0.5 2.5 2.5 0.5 25 200 Min. 15 25 40 3 3 -- -- Typ. -- -- -- -- -- 0.25 -- 0 0 2 2 -- -- -- Max. 35 60 100 -- -- 0.5 1.25 0.5 1.2 3.5 3.5 0.5 25 200 Min. 15 25 40 3 3 -- --
IDT59920A-7 Typ. -- -- -- -- -- 0.3 -- 0 0 3 3 -- -- -- Max. 35 60 100 -- -- 0.75 1.65 0.7 1.5 5 5 0.5 25 200 ns ns ns ns ns ns ns ns ms ps MHz Unit
Min. 15 25 40 3 3
(1,3,4)
Typ. -- -- -- -- -- 0.1 -- 0 0 2 2 -- -- --
FS = MED FS = HIGH
REF Pulse Width LOW(1,8) Zero Output Skew (All Outputs) Device-to-Device Skew(1,2,5) REF Input to FB Propagation Delay(1,7) Output Duty Cycle Variation from 50% Output Rise Time(1) Output Fall Time(1) PLL Lock Time(1,6) Cycle-to-Cycle Output Jitter(1) RMS Peak-to-Peak
(1)
-- --
-0.25 -0.5
0.5 0.5 -- -- --
-0.5 -1.2
0.5 0.5 -- -- --
-0.7 -1.5
0.5 0.5 -- -- --
NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. Guaranteed by design and characterization, not subject to production testing. 2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. 3. tSKEW is the skew between all outlets. See AC TEST LOADS. 4. For IDT59920A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.45ns Max. 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tPD is measured with REF input rise and fall times (from 0.2VDD to 0.8VDD ) of 1.5ns. 8. Refer to INPUT TIMING REQUIREMENTS for more detail.
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IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
VDD
VD D 80% Vth = 0.5VDD
1.5ns
1.5ns
100 Outpu t
20% 0V
100
CL
CMOS Input Test Waveform
CL = 50pF (CL = 30pF for -2 and -5 de vice s)
Test Load
tORISE tOFAL L
0.8 VDD
0.2 V DD
CMOS Output Waveform
AC TIMING DIAGRAM
tREF tRPW H REF tRPWL
tPD
tOD CV
tODCV
FB
tJR Q
tSKEW
tSKEW
OTHER Q
NOTES: Skew: tSKEW: tDEV: tODCV: tLOCK:
The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with VDD/2. The skew between all outputs. The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.) The deviation of the output from a 50% duty cycle. The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
tORISE and tOFALL are measured between 0.2VDD and 0.8VDD.
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IDT59920A LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
Blank I SO
Commercial (0C to +70C) Industrial (-40C to +85C) Small Outline IC (300-mil)
59920A-2 Low Skew PLL Clock Driver TurboClock Jr. 59920A-5 59920A-7
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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